Field of the Invention
The present invention relates to a drawing method which uses a charged particle beam, and a method of manufacturing an article.
Description of the Related Art
With an increase in packing density of semiconductor integrated circuits, and downsizing of semiconductor devices, it is desired to accelerate the development of the lithography technology. When the minimum pattern size has come close to the wavelength of a light source used for exposure in response to the progress of the photolithography technology, unintended light interactions occur between adjacent patterns. However, while the wavelength of a light source used in the photolithography process remains 193 nm, the minimum pattern size has come close to 22 nm these days. The reliability of the lithography process degrades as the difference between the minimum pattern size and the wavelength of light used in the photolithography process increases.
Light beams from respective patterns on a mask used in photolithography generate interference fringes upon mutual interactions. Due to factors associated with interference fringes generated by adjacent patterns, an unintended pattern may be formed on a wafer by chance, or a required pattern may be removed by accident. In either case, a pattern different from a desired pattern may be formed by exposure, leading to a device breakdown. A correction method such as optical proximity effect correction (OPC) is intended to predict the influence of adjacent patterns on each other, and correct a mask so as to form a desired pattern by exposure. However, as the minimum pattern becomes finer, light interactions become more complex, and their prediction quality degrades in optical proximity effect correction along with this trend.
As a method of solving the above-mentioned problem, a device design rule stipulating a pattern that has a constant width and extends in a limited direction (to be referred to as a 1D layout hereinafter) has been proposed in Proc. of SPIE, Vol. 7641, 764109-1. A practical manufacturing method will be described with reference to FIG. 10. FIG. 10 shows a photolithography process for a 22-nm generation SRAM gate cell using an exposure apparatus equipped with a light source having a wavelength of 193 nm, and an immersion optical system. Steps in this process will be described below.
[Step 1] A line-and-space pattern having a half pitch of 44 nm is formed by exposure using the exposure apparatus.
[Step 2] After the pattern formed by exposure is directly processed, or the underlayer is processed, a film is isotropically formed on the entire surface, and anisotropic etching is performed to form a hard mask having a line-and-space pattern with a half pitch of 22 nm while leaving the side wall, that is, the contour of the pattern intact. In step 2, a double patterning technique which uses a side wall is employed.
[Step 3] A resist is applied onto the hard mask, and cut hole patterns are formed on it by exposure.
[Step 4] The hole patterns formed by exposure are chemically treated to shrink them.
[Step 5] Anisotropic etching is performed again to form a hard mask having a desired gate cell pattern.
The shape of a 1D layout will be described with reference to FIG. 9C. FIG. 9C shows isolation regions and gate regions. The gate regions are formed on the isolation regions. A one-dimensional (1D) line-and-space pattern (L/S) is formed in each isolation region to extend in the X-direction, while a one-dimensional (1D) line-and-space pattern (L/S) is formed in each gate region to extend in the Y-direction. In this case, the gate regions will be described upon defining the isolation regions as an underlayer. To form various transistors, it is necessary to cut the gate regions using cut patterns. This requires the condition in which entrance of the end portions of the gate regions in the Y-direction, which are cut using the cut patterns, into active regions is prevented in accordance with the size accuracy and overlay accuracy. When this entrance into active regions occurs, a source/drain (S/D) region to be isolated between the right and left gates short-circuits, as shown in FIG. 9A. In the X-direction, the cut patterns must cover the cut portions of the gate regions as a whole, and must not come into contact with adjacent gate regions, as shown in FIG. 9B. Note that adjacent cut patterns may be connected to each other. In this manner, cut patterns need to neither be arranged symmetrically with respect to the pattern formed in the underlayer, nor have symmetry with each other. As long as the above-mentioned condition is satisfied, the arrangement has a given degree of freedom and need not have a given regularity.
Even when an exposure apparatus including a light source with a wavelength of 193 nm, and an immersion optical system is employed, the double patterning technique must be used to form a line-and-space pattern having a half pitch of 22 nm, so it is difficult to form cut hole patterns by exposure as well. This makes it necessary to add a step of shrinking the formed pattern, as in step 4. As a result, the numbers of masks and steps increase, so the throughput of the photolithography process lowers, leading to a rise in cost and degradation in reliability.